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CAD Engineer – Custom Signoff Lead (Physical Verification)

Full Time
San Diego, CA
Posted Today
Job description


Posted: Jul 27, 2022 Role Number: 200385543 Do you love building elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices! The Signoff Engineer ensures that all necessary and appropriate verification and analysis work has been performed on a complex mixed-signal design prior to tapeout. In this highly visible role as a core team member in our advanced Signoff CAD Group, you will enhance your career working on innovative designs. You’ll apply your hands-on experience in Custom layout and analysis to develop/define & refine the signoff methodologies for transistor level as well as gate level designs. The areas will include Physical Verification flows, Design and Layout rules, Extraction, PDK and foundry requirements, and IP for reuse. You will contribute to the definition of signoff requirements early in the project, work with other teams in the organization (Design, CAD and Technology) to verify that the EDA flows and tools are set up and run correctly during the project, and all signoff criteria are met at the end of the project. Responsibility also includes directly collaborating with design groups and providing frontline support for enablement / enhancement / debug requests.

Key Qualifications

  • Solid understanding of circuit design principles
  • Experience with Physical Verification tools and back-end flows
  • Experience in analog and mixed-signal layout, simulation, and extraction
  • Experience with chip integration including analog IP
  • Experience in analog and mixed signal designs
  • Strong understanding of CAD flows
  • Proficiency in programming/scripting languages (Python / Perl / C)
  • Strong verbal and written communications skills


Determine signoff criteria, work with technology and design teams Participate in technology and design reviews Develop and maintain signoff checks Verify CAD flows are generating correct results (flow signoff) Evaluate designs for signoff Drive signoff reviews with design teams Enablement of design teams on signoff infrastructure including page generation, build list maintenance, and enhancement request tracking achievement and signoff scheduling Ability to work in a demanding, team-oriented environment

Education & Experience

BSEE with 5 yrs. experience or MSEE with 2 yrs. experience

Additional Requirements

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